Digital-to-analog converter with embedded minimal error adaptive slope compensation for digital peak current controlled switched mode power supply

ABSTRACT

A method may include controlling switching behavior of switches of a switch-mode power supply based on a desired physical quantity associated with the switch-mode power supply, wherein the desired physical quantity is based at least in part on a slope compensation signal and generating the slope compensation signal to have a compensation value of approximately zero at an end of a duty cycle of operation of the switch-mode power supply.

RELATED APPLICATION

The present disclosure claims priority to U.S. Provisional PatentApplication Ser. No. 62/596,335, filed Dec. 8, 2017, which isincorporated by reference herein in its entirety.

FIELD OF DISCLOSURE

The present disclosure relates in general to circuits for electronicdevices, including without limitation personal audio devices such aswireless telephones and media players, and more specifically, to adigital-to-analog converter (DAC) with embedded minimal error adaptiveslope compensation for a digital peak current controlled switched modepower supply.

BACKGROUND

Personal audio devices, including wireless telephones, such asmobile/cellular telephones, cordless telephones, mp3 players, and otherconsumer audio devices, are in widespread use. Such personal audiodevices may include circuitry for driving a pair of headphones or one ormore speakers. Such circuitry often includes a speaker driver includinga power amplifier for driving an audio output signal to headphones orspeakers. Oftentimes, a power converter may be used to provide a supplyvoltage to a power amplifier in order to amplify a signal driven tospeakers, headphones, or other transducers. A switching power converteris a type of electronic circuit that converts a source of power from onedirect current (DC) voltage level to another DC voltage level. Examplesof such switching DC-DC converters include but are not limited to aboost converter, a buck converter, a buck-boost converter, an invertingbuck-boost converter, and other types of switching DC-DC converters.Thus, using a power converter, a DC voltage such as that provided by abattery may be converted to another DC voltage used to power the poweramplifier.

Often, boost converters operate as peak current-controlled boostconverters, wherein a main control loop of a control system is used todetermine a peak current requirement on each switching phase of theboost converter in order to generate a desired boosted output voltage ofthe boost converter. For boost duty cycles where a duty cycle (e.g.,which may be determined by subtracting an arithmetic ratio from thenumber one, wherein the arithmetic ratio equals the input voltagesupplied to the boost converter divided by the boost output voltage ofthe boost converter) is greater than 50%, slope compensation circuitrymay be required to avoid sub-harmonic behavior of the boost converter.Also present in many boost converter control systems is protectioncircuitry to ensure that the current of a boost converter is maintainedbelow a maximum value. The detection of the peak current in accordancewith the main control loop and detection of the maximum allowablecurrent is often performed by two separate circuits: a first comparatorcomparing a measured current (e.g., measured current of a power inductorof the boost converter) with a slope-compensated target peak currentsignal and a second comparator comparing the measured current to themaximum current limit. The main control loop, which may also be known asa compensator, may generate a target peak current signal which may bemodified by slope compensation circuitry, and such slope-compensatedtarget peak current signal may be compared by the first comparator tothe measured current in order to perform peak-current control of a boostconverter. However, because slope compensation may occur in analogcircuitry, an unknown amount of correction may exist at the point thefirst comparator toggles. Such error may be removed by the main controlloop in regulating the boosted voltage output by the power converter.

However, for duty cycles greater than 50%, without slope compensation,unstable oscillation may occur as a result of a sub-harmonicoscillation. However, such slope compensation may negatively affect adynamic range of a compensator digital-to-analog converter of a controlloop, as described in greater detail below, because the slopecompensation signal adds a varying correction term that varies with dutycycle, further complicated by the fact that duty cycle may varysignificantly in operation, and further complicated by the fact that ifthe slope-compensation term may be non-zero at the point that inductorcurrent I_(L) reaches slope-compensated peak current signal I_(PK)′.

SUMMARY

In accordance with the teachings of the present disclosure, one or moredisadvantages and problems associated with existing approaches tooperating a power converter may be reduced or eliminated.

In accordance with embodiments of the present disclosure, a method mayinclude controlling switching behavior of switches of a switch-modepower supply based on a desired physical quantity associated with theswitch-mode power supply, wherein the desired physical quantity is basedat least in part on a slope compensation signal and generating the slopecompensation signal to have a compensation value of approximately zeroat an end of a duty cycle of operation of the switch-mode power supply.

In accordance with these and other embodiments of the presentdisclosure, a system may include control circuitry configured to controlswitching behavior of switches of a switch-mode power supply based on adesired physical quantity associated with the switch-mode power supply,wherein the desired physical quantity is based at least in part on aslope compensation signal and a slope generator configured to generatethe slope compensation signal to have a compensation value ofapproximately zero at an end of a duty cycle of operation of theswitch-mode power supply.

Technical advantages of the present disclosure may be readily apparentto one skilled in the art from the figures, description and claimsincluded herein. The objects and advantages of the embodiments will berealized and achieved at least by the elements, features, andcombinations particularly pointed out in the claims.

It is to be understood that both the foregoing general description andthe following detailed description are examples and explanatory and arenot restrictive of the claims set forth in this disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present embodiments and advantagesthereof may be acquired by referring to the following description takenin conjunction with the accompanying drawings, in which like referencenumbers indicate like features, and wherein:

FIG. 1 illustrates an example personal audio device, in accordance withembodiments of the present disclosure;

FIG. 2 illustrates a block diagram of selected components of an exampleaudio integrated circuit of a personal audio device, in accordance withembodiments of the present disclosure;

FIG. 3 illustrates a block diagram of selected components of an examplepeak-current control boost converter with peak current limit controlwhich may be used to implement the power supply shown in FIG. 2, inaccordance with embodiments of the present disclosure;

FIG. 4 illustrates graphs depicting example waveforms of inductorcurrent and a slope compensation signal which illustrates the operatingprinciple for slope compensation of a peak current controlled switchedmode power supply, in accordance with embodiments of the presentdisclosure;

FIG. 5 illustrates graphs depicting example waveforms of inductorcurrent which illustrates the operating principle for peak currentcontrolled switched mode power supply without slope compensation, inaccordance with embodiments of the present disclosure;

FIG. 6 illustrates graphs depicting example waveforms of inductorcurrent and a slope compensation signal which further illustrates theoperating principle for slope compensation of a peak current controlledswitched mode power supply, in accordance with embodiments of thepresent disclosure;

FIG. 7 illustrates a block diagram of selected components of an examplesawtooth ramp generator that may provide a variable slope and atime-zero offset, in accordance with embodiments of the presentdisclosure;

FIG. 8 illustrates a block diagram of selected components of an examplesawtooth ramp generator that may automatically determine a time-zerooffset needed for a minimal error zero crossing, in accordance withembodiments of the present disclosure;

FIG. 9 illustrates a block diagram of selected components of an examplesawtooth ramp generator utilizing its amplifier as an active integrator,in accordance with embodiments of the present disclosure;

FIG. 10 illustrates a timing diagram of various switch control signals,clock control signals, and resultant voltage waveforms for the examplesawtooth ramp generator shown in FIG. 9, in accordance with embodimentsof the present disclosure;

FIG. 11 illustrates a timing diagram of various switch control signals,clock control signals, and resultant voltage waveforms for the examplesawtooth ramp generator shown in FIG. 9 with precharging that assumes afixed duty cycle, in accordance with embodiments of the presentdisclosure;

FIG. 12 illustrates a timing diagram of various switch control signals,clock control signals, and resultant voltage waveforms for the examplesawtooth ramp generator shown in FIG. 9 with precharging that utilizes aquasi-static duty cycle, in accordance with embodiments of the presentdisclosure;

FIG. 13 illustrates a block diagram of selected components of an examplecircuit with a sawtooth ramp generator utilizing its amplifier as anactive integrator, a digital-to-analog converter, and an analog summer,in accordance with embodiments of the present disclosure; and

FIG. 14 illustrates a timing diagram of various switch control signals,clock control signals, and resultant voltage waveforms for the examplecircuit shown in FIG. 13, in accordance with embodiments of the presentdisclosure.

DETAILED DESCRIPTION

FIG. 1 illustrates an example personal audio device 1, in accordancewith embodiments of the present disclosure. FIG. 1 depicts personalaudio device 1 coupled to a headset 3 in the form of a pair of earbudspeakers 8A and 8B. Headset 3 depicted in FIG. 1 is merely an example,and it is understood that personal audio device 1 may be used inconnection with a variety of audio transducers, including withoutlimitation, headphones, earbuds, in-ear earphones, and externalspeakers. A plug 4 may provide for connection of headset 3 to anelectrical terminal of personal audio device 1. Personal audio device 1may provide a display to a user and receive user input using a touchscreen 2, or alternatively, a standard liquid crystal display (LCD) maybe combined with various buttons, sliders, and/or dials disposed on theface and/or sides of personal audio device 1. As also shown in FIG. 1,personal audio device 1 may include an audio integrated circuit (IC) 9for generating an analog audio signal for transmission to headset 3and/or another audio transducer.

FIG. 2 illustrates a block diagram of selected components of an exampleaudio IC 9 of a personal audio device, in accordance with embodiments ofthe present disclosure. As shown in FIG. 2, a microcontroller core 18may supply a digital audio input signal DIG_IN to a digital-to-analogconverter (DAC) 14, which may convert the digital audio input signal toan analog signal V_(IN). DAC 14 may supply analog signal V_(IN) to anamplifier 16 which may amplify or attenuate audio input signal V_(IN) toprovide a differential audio output signal V_(OUT), which may operate aspeaker, a headphone transducer, a line level signal output, and/orother suitable output. In some embodiments, DAC 14 may be an integralcomponent of amplifier 16. A power supply 10 may provide the powersupply rail inputs of amplifier 16. In some embodiments, power supply 10may comprise a switched-mode power converter, as described in greaterdetail below. Although FIGS. 1 and 2 contemplate that audio IC 9 residesin a personal audio device, systems and methods described herein mayalso be applied to electrical and electronic systems and devices otherthan a personal audio device, including audio systems for use in acomputing device larger than a personal audio device, an automobile, abuilding, or other structure.

FIG. 3 illustrates a block diagram of selected components of an examplepeak-current controlled boost converter 20 which may be used toimplement power supply 10 shown in FIG. 2, in accordance withembodiments of the present disclosure. As shown in FIG. 3, boostconverter 20 may include a battery 22, a power inductor 30, a switch 28implemented as an n-type metal-oxide-semiconductor field-effecttransistor (NFET), a switch 29 implemented as a p-typemetal-oxide-semiconductor field-effect transistor (PFET), and a controlcircuit 32.

In a first phase of a switching cycle of boost converter 20, controlcircuit 32 may cause switch 28 to be activated (e.g., closed, turned on,enabled) and switch 29 to be deactivated (e.g., opened, turned off,disabled). Thus, during the first phase, a switch node (labeled as “SW”in FIG. 3) may be effectively shorted to a ground potential, such thatbattery 22 applies its voltage V_(BAT) across terminals of powerinductor 30. As a result, an inductor current I_(L) flowing in powerinductor 30 may increase during the first phase. As described in greaterdetail below, control circuit 32 may cause inductor current I_(L) toincrease until such point that inductor current I_(L) reaches aslope-compensated peak current limit I_(PK)′, at which the first phasemay end.

In a second phase of the switching cycle of boost converter, controlcircuit 32 may cause switch 28 to be deactivated and switch 29 to beactivated. As a result, inductor current I_(L) may decrease during thesecond phase as power inductor 30 discharges into boost capacitor 26,boosting the supply voltage V_(SUPPLY) to a voltage higher than batteryvoltage V_(BAT). The second phase may continue until the end of theswitching cycle, after which the first phase again occurs. In someembodiments, control circuit 32 may deactivate switch 29 during thesecond phase, such that a body diode of the PFET implementing switch 29conducts inductor current I_(L).

As shown in FIG. 3, control circuit 32 may include a compensator 34,current sensor circuit 36, a digital-to-analog converter (DAC) 38, aslope generator 42, a peak current comparator 44, a clock (CLK)generator 46, a latch 48, and switch control block 50.

In operation, the duty cycle of switch 28 (e.g., the duration of thefirst phase) control circuit 32 may determine the magnitude of supplyvoltage V_(SUPPLY) relative to battery voltage V_(BAT). For example, theduty cycle D needed to provide a desired supply voltage V_(SUPPLY) maybe given by D=1−V_(BAT)/V_(SUPPLY). Thus, for a desired level of supplyvoltage V_(SUPPLY) (e.g., which may be based on an envelope of an outputsignal of an amplifier), control circuit 32 may implement a feedbackcontrol loop, which may be internal to compensator 34, based on measuredsupply voltage V_(SUPPLY) and measured inductor current I_(L), which maybe measured by current sensor circuit 36 (e.g., using a sense resistorwith resistance R_(SENSE); in some embodiments, R_(SENSE) may have aresistance of approximately 10 me). Thus, control circuit 32 may monitoractual supply voltage V_(SUPPLY), compare it against a desired supplyvoltage V_(SUPPLY), and increase or decrease actual supply voltageV_(SUPPLY) by increasing or decreasing the peak of inductor currentI_(L). In that vein, compensator 34 may generate a digital signalindicative of a desired peak current, and DAC 38 may convert suchdigital signal into an analog equivalent peak current signal I_(PK).Slope generator 42 may generate a slope compensation signal. In someembodiments, slope generator 42 may generate the slope compensationsignal as a triangle or sawtooth waveform. The slope compensation signalmay be combined with peak current signal I_(PK) to generateslope-compensated peak current signal I_(PK)′. Peak current comparator44 may, during the first phase, compare a measured inductor currentI_(L) (e.g., measured by a current sensor circuit 36), generating acontrol signal responsive to the comparison. Together, the output ofcomparator 44, clock generator 46, and latch 48 may be arranged asshown, or arranged in another suitable manner, to generate a controlsignal to switch control block 50. For example, clock generator 46 maygenerate a clock signal indicating the beginning of a switching cycle(e.g., beginning of the first phase) and comparator 44 may, based on apoint in which measured inductor current I_(L) reaches slope-compensatedpeak current signal I_(PK)′, generate a signal indicating the end of thefirst phase. Based on such signals indicating timing of switch cyclesand switch phases of boost converter 20, latch 48 may generateappropriate control signal(s) to switch control block 50, which may inturn generate appropriate control signals to switches 28 and 29 toaccordingly selectively activate and deactivate switches 28 and 29.

As disclosed above, boost converter 20 may employ a slope generator 42for generating a slope compensation signal. FIG. 4 illustrates graphsdepicting example waveforms of sensed inductor current I_(L) and a slopecompensation signal I_(comp) which illustrates the operating principlefor slope compensation of a peak current controlled switched mode powersupply (e.g., such as boost converter 20), in accordance withembodiments of the present disclosure. In operation, each switchingcycle of the peak current controlled switched mode power supply isstarted with a known timing reference and detects when the peak of thesensed inductor current I_(L) crosses a threshold (e.g., as determinedby comparator 44) during its energizing phase (e.g., in which switch 28is activated and switch 29 is deactivated). The energizing phase isshown in FIG. 4 as having a duration of time T_(on). At the point thatthe peak of the sensed inductor current I_(L) crosses the threshold, theswitched mode power supply may synchronously switch to its dischargephase (e.g., in which switch 28 is deactivated and switch 29 isactivated) in which energy stored in inductor 30 may replenish charge incapacitor 26. The discharge phase is shown in FIG. 4 as having aduration of time T_(off). Thus, slope compensation signal I_(comp)serves effectively as a signal that, during each switching cycle,decreases from a known starting value to a known ending value, setting apeak current limit that decreases during the duration of a switchingcycle.

To further illustrate the desire for implementing slope compensation,reference is made to FIG. 5, which depicts unstable oscillation that mayoccur as a result of a sub-harmonic oscillation in the absence of slopecompensation for duty cycles greater than 50%. FIG. 5 depicts with asolid line an ideal inductor current I_(L) and with a dotted line anactual inductor current I_(L) which may result from a disturbanceintroduced to such inductor current I_(L) (e.g., via electrical noise).Such disturbance may cause actual inductor current I_(L) to, inalternating cycles, reach peak current signal I_(PK) too soon within acycle or too late within a cycle, leading to an unstable sub-harmonicoscillation, and a situation in which a volt-second balance betweenadjacent cycles of boost converter 20 is not maintained.

As noted above, to overcome these problems and disadvantages, slopegenerator 42 may add a saw-tooth signal to the peak current signalI_(PK) to generate slope-compensated peak current signal I_(PK)′ whichmay have the effect of biasing the current-control loop to the properduty cycle. Thus, as shown in FIG. 6, during the energizing phase ofboost converter 20, inductor current I_(L) may increase until it reachesslope-compensated peak current signal I_(PK)′, and then decrease duringthe discharging phase of boost converter 20. The effect ofslope-compensated peak current signal I_(PK)′ may be to lengthen theenergizing phase in situations in which the energizing phase would lastfor less than the desired duty cycle in the absence of slopecompensation, and to shorten the energizing phase in situations in whichthe energizing phase would last for more than the desired duty cycle inthe absence of slope compensation.

However, slope compensation as depicted in FIG. 6 may have somedisadvantages. Such slope compensation may negatively affect the dynamicrange of compensator 34 and DAC 38, as the slope compensation signaladds a varying correction term that varies with duty cycle, furthercomplicated by the fact that duty cycle may vary significantly inoperation, and further complicated by the fact that if theslope-compensation term is non-zero at the point that inductor currentI_(L) reaches slope-compensated peak current signal I_(PK)′, compensator34 and DAC 38 must remove the non-zero value to ensure accuracy. Theslope compensation scheme in FIG. 6 may also have undesirable startuptransients.

To overcome these and/or other disadvantages associated withimplementing a slope compensated peak current controlled switched modepower converter, it may be desirable to generate a sawtooth ramp forslope compensation ramp I_(ramp) with a cycle-by-cycle adaptable slopeand a time-zero offset applied at the beginning of a switching cycle inorder for the required slope to provide a zero crossing at a requiredduty cycle for the switched mode power converter, as described ingreater detail below. These variable attributes for slope compensationramp I_(ramp) may result in a smooth start-up for the switched modepower converter, a peak current signal I_(PK) that may accuratelyreflect an actual peak inductor current for each switching cycle, andrelaxed dynamic range requirements for DAC 38.

FIG. 7 illustrates a block diagram of selected components of an examplesawtooth ramp generator 42A that may approach the desired attributes ofvariable slope and time-zero offset, in accordance with embodiments ofthe present disclosure. In operation, example sawtooth ramp generator42A may implement all or a part of slope generator 42 depicted in FIG.3. As shown in FIG. 7, sawtooth ramp generator 42A may include avariable current source 80 having a variable current to define a slopefor a ramp signal V_(ramp) (which may be representative of or may beused to generate slope compensation ramp I_(ramp)), a capacitor 82 inseries with variable current source 80, and a reset switch 84 inparallel with capacitor 82. Sawtooth ramp generator 42A may also includean amplifier comprising an operational amplifier 86, an input resistor88 with input resistance R_(i) coupled between an inverting inputterminal of operational amplifier 86 and the output of variable currentsource 80, a feedback resistor 90 with feedback resistance R_(f) coupledbetween the inverting terminal input terminal of operational amplifier86 and an output terminal of operational amplifier 86, and a variablevoltage source 92 coupled to the non-inverting input of operationalamplifier 86 for generating a variable common-mode voltage V_(cm). Inoperation, switch 84 may briefly activate at the beginning of eachswitching cycle to set a voltage across capacitor 82 to zero at thebeginning of the switching cycle. During the switching cycle, variablecurrent source 80 may increase the voltage across capacitor 82 with aslope proportional to the variable current generated by variable currentsource 80, which in turn causes ramp signal V_(ramp) to decrease from amaximum voltage at the beginning of the switching cycle to common-modevoltage V_(cm) in accordance with the slope.

Accordingly, sawtooth ramp generator 42A may operate in one of two waysbased on a calculated duty cycle determined based on monitoring of aninput voltage (e.g., battery voltage V_(BAT)) and an output voltage(e.g., supply voltage V_(SUPPLY)) for boost converter 20. As an example,for boost converter 20, a duty cycle D may be calculated asD=1−(V_(BAT)/V_(SUPPLY)). The two ways sawtooth ramp generator 42A mayoperate include:

1. Setting common-mode voltage V_(cm) for a given slope setting suchthat the zero crossing of common-mode voltage V_(cm) occurs at the 50%duty cycle point of the switched mode power supply.

2. Setting common-mode voltage V_(cm) for a given slope setting suchthat the zero crossing of common-mode voltage V_(cm) occurs at anexpected duty cycle of the switched mode power supply.

The first manner of operation may require a correction at the output ofa compensator (e.g., compensator 34) to adjust for the actual duty cycleof the switched mode power supply. Such correction may reduce a dynamicrange requirement and error of the peak current value I_(PK) generatedby DAC 38, but significant error may remain by using this approach. Thesecond manner of operation may achieve optimal dynamic range for DAC 38and minimal error in its estimate of peak current I_(PK), but only forsteady-state operation and fixed input/output voltage conditions.

Having to adjust a zero-crossing level of common-mode voltage V_(cm) mayleave unacceptable error in the switched mode power supply and/or mayadd more variables that must be managed in the switched mode powersupply to achieve minimal slope compensation error. It may be desired toonly set the slope and let the slope compensation generation circuitautomatically determine a time-zero offset as needed for the minimalerror zero crossing. Such automatic determination may eliminate the needfor adjusting the zero crossing via the reference adjustment ofcommon-mode voltage V_(cm) used in the second manner of operation forsawtooth ramp generator 42A described above. Such automaticdetermination may also eliminate error in the peak current value I_(PK)generated on a cycle-by-cycle basis. FIG. 8 illustrates a block diagramof selected components of an example sawtooth ramp generator 42B thatmay perform such automatic determination, in accordance with embodimentsof the present disclosure. In operation, example sawtooth ramp generator42B may implement all or a part of slope generator 42 depicted in FIG.3.

In other words, FIG. 8 depicts a sawtooth ramp generator 42B forapplying a variable common-mode V_(cm) and slope for the sawtooth ramp.Such slope may be determined in any suitable manner. For example, insome embodiments, control circuit 32 may perform a feedforwardcalculation of the duty cycle by measurement of battery voltage V_(BAT)and supply voltage V_(SUPPLY). Together, these measured voltages may beused to determine the appropriate slope and the time at which azero-crossing should occur.

Example sawtooth ramp generator 42B depicted in FIG. 8 may be identicalin many respects to example sawtooth ramp generator 42A of FIG. 7, andthus, only the material differences between example sawtooth rampgenerator 42B and example sawtooth ramp generator 42A are described indetail. As compared to example sawtooth ramp generator 42A of FIG. 7,example sawtooth ramp generator 42B of FIG. 8 may include the use of twoadditional capacitors 96 in a ping-pong fashion for setting common-modevoltage V_(cm). In a first switching cycle, capacitor 94 may be coupledto the non-inverting terminal of operational amplifier 86 (e.g., viaswitch 98 when switch 98 is activated), and capacitor 96 may beprecharged (e.g., via switch 106 when switch 106 is activated) fromcurrent source 102 which may be a current mirror of variable currentsource 80. Thus, capacitor 94 may be precharged with the sameintegrating current source over the same duration as capacitor 82. In asecond switching cycle (operation may alternate between the firstswitching cycle and the second switching cycle), capacitor 96 may becoupled to the non-inverting terminal of operational amplifier 86 (e.g.,via switch 100 when switch 100 is activated), and capacitor 94 may beprecharged (e.g., via switch 104 when switch 104 is activated) fromcurrent source 102 which, as noted above, may be a current mirror ofvariable current source 80. Thus, capacitor 96 may be precharged withthe same integrating current source over the same duration as capacitor82. Accordingly, when current source 102 is a simple mirror of 80,common-mode voltage V_(cm) may be determined by the on time of currentsource 102 (e.g., which may be related to the duty cycle of boostconverter 20). For example, if current source 102 is active (via theswitches below called “pre”), then capacitor 94 may be precharged forthe on time of switch 28 in FIG. 3, using the same current level thatmay be used to discharge capacitor 94 in the next switching period, sothat the starting point for capacitor 94 in each switching cycle mayensure that a zero crossing occurs at the end of the on time of switch28 in the next switching cycle, assuming steady state behavior.

During a switching cycle when capacitor 94 is precharged, a reset switch108 in parallel with capacitor 94 may be briefly activated to dischargecapacitor 94 to zero volts. Likewise, during a switching cycle whencapacitor 96 is precharged, a reset switch 110 in parallel withcapacitor 96 may be briefly activated to discharge capacitor 96 to zerovolts. Such reset-and-pre-charge operation of capacitors 94 and 96 mayresult in an automatic setting of the common-mode voltage V_(cm), andthus an automatic setting of a time-zero offset and resulting zerocrossing for ramp signal V_(ramp) for a given setting of the slope bythe variable current of variable current source 80.

FIG. 9 illustrates a block diagram of selected components of an examplesawtooth ramp generator 42C utilizing its amplifier as an activeintegrator, in accordance with embodiments of the present disclosure. Inoperation, example sawtooth ramp generator 42C may implement all or apart of slope generator 42 depicted in FIG. 3. Example sawtooth rampgenerator 42C depicted in FIG. 9 may be identical in many respects toexample sawtooth ramp generator 42B of FIG. 8, and thus, only thematerial differences between example sawtooth ramp generator 42C andexample sawtooth ramp generator 42B are described in detail. Onematerial difference is that in example sawtooth ramp generator 42C, theamplifier is used as an active integrator, and thus only two capacitors94A and 96A (instead of the three required in example sawtooth rampgenerator 42B) are needed to implement the optimal slope compensationcircuit, which thus may require a smaller physical space as compared toexample sawtooth ramp generator 42B. The solution of example sawtoothramp generator 42C may also eliminate a signal-dependent common-modeshift on the inputs of operational amplifier 86.

FIG. 10 illustrates a timing diagram of various switch control signals(e.g., ramp1, rst1, pre1, ramp2, rst2, pre2) and resultant voltagewaveforms for a voltage V_(c1) across capacitor 94A, voltage V_(c2)across capacitor 96A, and ramp signal V_(ramp), in accordance withembodiments of the present disclosure. FIG. 10 also depicts an exampleclock signal Clk_sw defining a switching period for a switched modepower source, and a clock signal Clk_pwm defining a pre-charging periodfor pre-charging capacitors 94A and 96A. As depicted in FIG. 9, examplesawtooth ramp generator 42C may include a plurality of switches 112,114, 116, 118, 120, 122, 124, 126, 128, 130, and 132 arranged as shownand wherein:

-   -   Switch 112 may be active when either of control signal rst1 or        control signal pre1 is asserted;    -   Switch 114 may be active when either of control signal rst2 or        control signal pre2 is asserted;    -   Switch 116 may be active when control signal rst1 is asserted;    -   Switch 118 may be active when control signal rst2 is asserted;    -   Switch 120 may be active when control signal pre1 is asserted;    -   Switch 122 may be active when control signal pre2 is asserted;    -   Switch 124 may be active when control signal ramp1 is asserted;    -   Switch 126 may be active when control signal ramp1 is asserted;    -   Switch 128 may be active when control signal ramp2 is asserted;    -   Switch 130 may be active when control signal ramp2 is asserted;        and    -   Switch 132 may be active when either of control signal rst1 or        control signal rst2 is asserted.

Similar to example sawtooth ramp generator 42B, example sawtooth rampgenerator 42C may use two integrating capacitors 94A and 96A in aping-pong fashion. When capacitor 94A is coupled between the invertinginput terminal and output terminal of operation amplifier 86 to generateramp signal V_(ramp), capacitor 96A may be precharged using an equalcurrent source (e.g., current source 102) over the same duration as thecurrent ramp time. Capacitor 96A may then be coupled between theinverting input terminal and output terminal of operation amplifier 86to generate ramp signal V_(ramp) in the subsequent switching cycle whilecapacitor 94A is reset then pre-charged. As in example sawtooth rampgenerator 42B, in example sawtooth ramp generator 42C, thereset-and-pre-charge operation of capacitors 94A and 96A may result inan automatic setting of the common-mode voltage V_(cm), and thus anautomatic setting of a time-zero offset and resulting zero crossing forramp signal V_(ramp) for a given setting of the slope by the variablecurrent of variable current source 80.

Example sawtooth ramp generators 42A, 42B, and 42C may allow threeoptions for setting a time-zero offset and ramp signal V_(ramp) zerocrossing to achieve minimal error adaptive slope compensation in a peakcurrent controlled switched mode power supply. The choice among suchoptions may involve trade-offs in performance versus complexity. In someinstances, a combination of all three options may be used as needed tomeet various system-level requirements. Such options are described indetail below.

For the first option, as shown in the timing diagram of FIG. 11, astatic configuration may be utilized to set a zero crossing of rampsignal V_(ramp) at a fixed duty cycle (e.g., 50%). As shown in FIG. 11,a pre-charge time may be set by clock signal Clk_pre, which is depictedas being set to 50% duty cycle in the example of FIG. 11. However, theexample of FIG. 11 also depicts that the actual duty cycle is lower than50%. A timing error indicated in the diagram as “Error” may result thatmust be corrected for at the output of DAC 38 in order to achieve theactual duty cycle zero crossing.

For the second option, as shown in the timing diagram of FIG. 12, aquasi-static configuration may be utilized to set a zero crossing oframp signal V_(ramp) at the expected duty cycle for the switched modepower supply. In this case, an expected duty cycle may be set by controlcircuitry (not explicitly shown in the FIGURES), and as noted above, maybe calculated based on an input voltage and output voltage of theswitched mode power supply (e.g., for boost converters 20. duty cycle Dmay be calculated as D=1−(V_(BAT)/V_(SUPPLY))). The pre-charge time maybe by clock signal Clk_pre, which may be set to the expectedsteady-state duty cycle calculated as described. FIG. 12 depicts ascenario in which the expected duty cycle matches the actualsteady-state duty cycle resulting in zero timing error for the zerocrossing of ramp signal V_(ramp). Zero error in the approximation may beapproached by employing a delta-sigma loop (not explicitly shown in theFIGURES) to accurately set the expected duty cycle over multiple cycles.

For the second option, as shown in the timing diagram ofpreviously-described FIG. 10, a self auto-calibration may be utilized toset a zero crossing of ramp signal V_(ramp) at the duty cycle for theswitched mode power supply based on the duty cycle of at least one ormore previous switching cycles. As shown in FIG. 10, the pre-chargephase defined by clock signal Clk_pwm may be equal in duration to theenergizing phase of the power inductor of the switched mode power supply(e.g., inductor 30) to give a minimal error in the zero crossing of rampsignal V_(ramp). In this case, the pre-charge time may be set by apulse-width modulated signal derived from an actual pulse-widthmodulation control signal used to drive the switched mode power supply.

FIG. 13 illustrates a block diagram of selected components of an examplecircuit 42D combining into a single circuit a sawtooth ramp generatorutilizing its amplifier as an active integrator, a digital-to-analogconverter, and an analog summer, in accordance with embodiments of thepresent disclosure. Referring back to FIG. 3, three separate buildingblocks are used to generate the slope-compensated peak current controlsignal I_(PK)′: DAC 38, slope generator 42 (with ramp generator), and ananalog summer 43. As shown in FIG. 13, circuit 42D may combine a DAC 38having multiple DAC elements 134, sawtooth ramp generator 42C of FIG. 9,and summer 43 (effectively implemented by the electrical node of theinverting input of operational amplifier 86) into a single circuit.

FIG. 14 illustrates a timing diagram of various switch control signals(e.g., ramp1, rst1, pre1, ramp2, rst2, pre2) and resultant voltagewaveforms for voltage V_(c1) across capacitor 94A, voltage V_(c2) acrosscapacitor 96A, and slope-compensated peak current control signalI_(PK)′, in accordance with embodiments of the present disclosure. FIG.14 also depicts an example clock signal Clk_sw defining a switchingperiod for a switched mode power source, and a clock signal Clk_pwmdefining a pre-charging period for pre-charging capacitors 94A and 96A.

Although the foregoing contemplates use of current mirrors as currentsources, other suitable approaches may be used to implement sawtoothramp generators 42A-42C.

As used herein, when two or more elements are referred to as “coupled”to one another, such term indicates that such two or more elements arein electronic communication or mechanical communication, as applicable,whether connected indirectly or directly, with or without interveningelements.

This disclosure encompasses all changes, substitutions, variations,alterations, and modifications to the example embodiments herein that aperson having ordinary skill in the art would comprehend. Similarly,where appropriate, the appended claims encompass all changes,substitutions, variations, alterations, and modifications to the exampleembodiments herein that a person having ordinary skill in the art wouldcomprehend. Moreover, reference in the appended claims to an apparatusor system or a component of an apparatus or system being adapted to,arranged to, capable of, configured to, enabled to, operable to, oroperative to perform a particular function encompasses that apparatus,system, or component, whether or not it or that particular function isactivated, turned on, or unlocked, as long as that apparatus, system, orcomponent is so adapted, arranged, capable, configured, enabled,operable, or operative. Accordingly, modifications, additions, oromissions may be made to the systems, apparatuses, and methods describedherein without departing from the scope of the disclosure. For example,the components of the systems and apparatuses may be integrated orseparated. Moreover, the operations of the systems and apparatusesdisclosed herein may be performed by more, fewer, or other componentsand the methods described may include more, fewer, or other steps.Additionally, steps may be performed in any suitable order. As used inthis document, “each” refers to each member of a set or each member of asubset of a set.

Although exemplary embodiments are illustrated in the figures anddescribed below, the principles of the present disclosure may beimplemented using any number of techniques, whether currently known ornot. The present disclosure should in no way be limited to the exemplaryimplementations and techniques illustrated in the drawings and describedabove.

Unless otherwise specifically noted, articles depicted in the drawingsare not necessarily drawn to scale.

An examples and conditional language recited herein are intended forpedagogical objects to aid the reader in understanding the disclosureand the concepts contributed by the inventor to furthering the art, andare construed as being without limitation to such specifically recitedexamples and conditions. Although embodiments of the present disclosurehave been described in detail, it should be understood that variouschanges, substitutions, and alterations could be made hereto withoutdeparting from the spirit and scope of the disclosure.

Although specific advantages have been enumerated above, variousembodiments may include some, none, or all of the enumerated advantages.Additionally, other technical advantages may become readily apparent toone of ordinary skill in the art after review of the foregoing figuresand description.

To aid the Patent Office and any readers of any patent issued on thisapplication in interpreting the claims appended hereto, applicants wishto note that they do not intend any of the appended claims or claimelements to invoke 35 U.S.C. § 112(f) unless the words “means for” or“step for” are explicitly used in the particular claim.

What is claimed is:
 1. A method comprising: controlling switchingbehavior of switches of a switch-mode power supply based on a desiredphysical quantity associated with the switch-mode power supply, whereinthe desired physical quantity is based at least in part on a slopecompensation signal; and generating the slope compensation signal tohave a compensation value of approximately zero at an end of a dutycycle of operation of the switch-mode power supply, wherein generatingthe slope compensation signal includes causing the slope compensation tohave a starting value at a beginning of each duty cycle by configuringthe starting value over one or more switching cycles of the switch-modepower supply.
 2. The method of claim 1, wherein generating the slopecompensation signal includes causing the slope compensation to have astarting value at a beginning of the duty cycle based on an assumptionthat the switch-mode power supply has a fifty-percent duty cycle.
 3. Themethod of claim 1, wherein generating the slope compensation signalincludes setting a starting value for a switching cycle of theswitch-mode power supply based on a duty cycle of one or more previousswitching cycles of the switch-mode power supply.
 4. The method of claim1, wherein generating the slope compensation signal includes setting astarting value for a switching cycle of the switch-mode power supplybased on calculations for determining the duty cycle.
 5. The method ofclaim 4, wherein the calculations for determining the duty cycle arebased on a supply voltage to and an output voltage generated by theswitch-mode power supply.
 6. The method of claim 1, wherein generatingthe slope compensation signal includes using control signals associatedwith the switch-mode power supply to modify one or more previousswitching cycles of the switch-mode power supply prior to a switchingcycle of the switch-mode power supply in order to set the starting valuefor the switching cycle.
 7. The method of claim 1, wherein the desiredphysical quantity is a peak current associated with the switch-modepower supply.
 8. The method of claim 1, wherein the desired physicalquantity is a peak current associated with an inductor of theswitch-mode power supply.
 9. A system comprising: control circuitryconfigured to control switching behavior of switches of a switch-modepower supply based on a desired physical quantity associated with theswitch-mode power supply, wherein the desired physical quantity is basedat least in part on a slope compensation signal; and a slope generatorconfigured to generate the slope compensation signal to have acompensation value of approximately zero at an end of a duty cycle ofoperation of the switch-mode power supply, wherein generating the slopecompensation signal includes causing the slope compensation to have astarting value at a beginning of each duty cycle by configuring thestarting value over one or more switching cycles of the switch-modepower supply.
 10. The system of claim 9, wherein generating the slopecompensation signal includes causing the slope compensation to have astarting value at a beginning of the duty cycle based on an assumptionthat the switch-mode power supply has a fifty-percent duty cycle. 11.The system of claim 9, wherein generating the slope compensation signalincludes setting a starting value for a switching cycle of theswitch-mode power supply based on a duty cycle of one or more previousswitching cycles of the switch-mode power supply.
 12. The system ofclaim 9, wherein generating the slope compensation signal includessetting a starting value for a switching cycle of the switch-mode powersupply based on calculations for determining the duty cycle.
 13. Thesystem of claim 12, wherein the calculations for determining the dutycycle are based on a supply voltage to and an output voltage generatedby the switch-mode power supply.
 14. The system of claim 9, whereingenerating the slope compensation signal includes using control signalsassociated with the switch-mode power supply to modify one or moreprevious switching cycles of the switch-mode power supply prior to aswitching cycle of the switch-mode power supply in order to set thestarting value for the switching cycle.
 15. The system of claim 9,wherein the desired physical quantity is a peak current associated withthe switch-mode power supply.
 16. The system of claim 9, wherein thedesired physical quantity is a peak current associated with an inductorof the switch-mode power supply.